Random Process Variation in Deep-Submicron CMOS

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of fundamental randomness in the behavior of silicon structures where device operation must be described as a stochastic process. Electric noise due to the trapping and de-trapping of electrons in lattice defects may result in large current fluctuations, and those may be different for each device within a circuit. At this scale, a single dopant atom may change device characteristics, leading to large variations from device to device [2]. As the device gate length approaches the correlation length of the oxide-silicon interface, the intrinsic threshold voltage fluctuations induced by local oxide thickness variation will become significant [3]. Finally, line-edge roughness, i.e., the random variation in the gate length along the width of the channel, will also contribute to the overall variability of gate length [4]. Since placement of dopant atoms introduced into silicon crystal is random, the final number and location of atoms in the channel of each transistor is a random variable. As the threshold voltage of the transistor is determined by the number and placement of dopant atoms, it will exhibit a considerable variation [3]. This leads to variation in the transistors’ circuit-level properties, such as delay and power [5]. Predicting the timing uncertainty is traditionally done through corner-based analysis, which performs static timing analysis (STA) at multiple corners to obtain the extreme-case results. In each corner, process parameters are set at extreme points in the multidimensional space. As a consequence, the worst-case delay from the corner-based timing analysis is over pessimistic since it is unlikely for all process parameters to have extreme values at the same time. Additionally, the number of process corners grows exponentially as the number of process variations increases. Recently, statistical STA (SSTA) has been proposed as a potential alternative to consider process variations for timing verification. In contrast to static timing analysis, SSTA represents gate delays and interconnect delays as probability distributions, and provides the distribution (or statistical moments) of each timing